The present invention relates to a wafer-scale semiconductor integrated circuit device having a plurality of chips arranged on a wafer. Further, the present invention relates to a method for forming interconnection lines between chips on a wafer of a wafer-scale semiconductor integrated circuit device.
There is known a wafer-scale semiconductor integrated circuit device,-which has a plurality of chips formed on a single wafer of a semiconductor, such as a silicon wafer. Generally, all the chips on the wafer have the same function. Such a wafer-scale semiconductor device is suitable for application to a semiconductor integrated circuit memory. A wafer-scale semiconductor memory device has an extremely high storage capacity and high integration density.
As shown in FIG. 1, a wafer-scale semiconductor integrated circuit device has a plurality of chips 3 formed on a wafer 2. Internal connection lines of each of the chips 3 are formed using a reticle 1 as shown in FIG. 2. The reticle 1 in FIG. 2 has an internal connection line pattern part (area) 4, an exposure part (area) 5 and a light interrupt part (area) 6. The internal connection part 4 has internal connection line patterns formed of a chromium (Cr) film which functions to interrupt light. The exposure part 5 passes light and is formed by partially eliminating the chromium film. The exposure part 5 is formed so that it surrounds the internal connection part 4. The light interrupt part 6 formed of a light interrupt film, such as a chromium film, is formed so that it surrounds the exposure part 5. An exposure area on the wafer 2 is moved step by step by a stepper (a step and repeat process) so that a large number of chip patterns are depicted on a photoresist on the wafer. In this manner, a plurality of identical internal connection lines are formed on the wafer 2.
In a case where a plurality of single chip semiconductor devices are formed, the internal connection lines formed in the chips 3 are separated from each other by scribe lines 7, which are formed by double exposure of the exposure part 5 of the reticle 1 so that the chips 3 are separated from each other. On the other hand, when a wafer-scale semiconductor device is formed, interconnection lines which connect the chips 3 to each other are formed on the areas of the scribe lines 7.
Conventionally, such interconnection lines between the chips 3 are formed by the following processes. According to a first conventional process, an electron beam is projected onto the scribe lines 7 on the wafer 2 placed in an aluminum gaseous phase so that aluminum interconnection lines having predetermined patterns are grown on the scribe line areas 7. According to a second conventional process, a mask for forming interconnection lines between the chips 3 is formed by an electron beam exposure process. Then the wafer 2 is photo-etched using the mask so that interconnection lines between the chips 3 are formed. According to a third conventional process, the chips 3 are mutually connected by bonding wires.
However, the above-mentioned conventional processes have the following disadvantages. The first conventional process has a low throughput because interconnection lines between the chips 3 on the wafer 2 are defined directly by the electron beam. The second conventional process has a limited integration density because interconnection lines are formed by the photo-etching process using the mask, and in addition, reliability is not high because of the same reason. The third conventional process cannot provide a high integration density because interconnection lines are formed of bonding wires.
Chips located in the vicinity of a peripheral end of the wafer 2 have input terminals which are not connected to other chips and are in a floating (high impedance) state. For this reason, the input level of an input circuit in each of the chips located in the vicinity of the peripheral end of the wafer 2 is indefinite. The indefinite input level causes a through current passing through a CMOS circuit which forms the input circuit. This causes an increase in power consumption and a malfunction resulting from an external noise is caused.